"""
Copyright 2009, Thomas Dejanovic, Jay Shurtz
 
This is free software; you can redistribute it and/or modify it
under the terms of the GNU Lesser General Public License as
published by the Free Software Foundation; either version 2.1 of
the License, or (at your option) any later version.
 
This software is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public
License along with this software; if not, write to the Free
Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
02110-1301 USA, or see the FSF site: http://www.fsf.org.
"""

#-----------------------------------------------------------------

id = "$Id: verilog_net_dict.py 667 2010-07-01 00:12:17Z jayshurtz $"
# $URL: http://hatch.googlecode.com/svn/trunk/hatch/hatch_targets/verilog/verilog_net_dict.py $
# $Author: jayshurtz $
version = " ".join(id.split()[1:3])

#-----------------------------------------------------------------


#import to_hatch_structure
#from hatch_log import * # For error strings & logging.


class VerilogNet(object):
    """ A class to hold a verilog net.

        Types are defined in a set before use, so a type cannot be used before being defined.

        Widths are integers greater than 1 (probably?)

    """

    def __init__(self, owner, name, type, width, signed=False):
        """ 'owner' is the VerilogNetDict that is a dictionay of HdvVar.
        """
        self.owner = owner
        self.name  = name
        self.type  = type
        self.width = width
        self.signed = signed


    def __setattr__(self, name, value):
        if name == "owner" or name == "name":
            object.__setattr__(self, name, value)
        elif name == "type":
            if value not in self.owner.type_name_list:
                raise TypeError, "Unknown HDL var type being set for " + self.name
            else:
                try:
                    t = self.type
                except AttributeError: # we have not set this attibute yet, so set it.
                    object.__setattr__(self, name, value)
                    self.owner.type[value].append(self.name)
                else: # this attribute has been set, so remove it from
                      # the current type set and add it to the new
                      # type set.
                    self.owner.type[t].remove(self.name)
                    self.owner.type[value].append(self.name)
        elif name == "width":
            if type(value) is not int:
                raise TypeError, "attempting to set non int width for HDL var " + self.name
            else:
                object.__setattr__(self, name, value)
        elif name == "signed":
            if type(value) is not bool:
                raise TypeError, "attempting to set non boolean value for signed number flag " + self.name
            else:
                object.__setattr__(self, name, value)
        else:
            raise AttributeError, name  # <<< DON'T FORGET THIS LINE !!
        
        
#-----------------------------------------------------------------

class VerilogNetBlock(dict):
    """ A class for hdl variables in a given scope.

        setting the same key twice is not allowed.  Each key has a
        width and a type.

        each element is a 2 element touple with the first being the
        type and the second element being the elementdictionary with
        type and width as the key.

        types are defined in a list before use, so a type cannot be
        used before being defined.

        widths are integers greater than 1 (probably?)
    """

    def addType(self, t):
        if t not in self.type_name_list :
            self.type_name_list.append(t)
            self.type[t] = []

    def __init__(self):
        dict.__init__(self)
        self.type_name_list = []
        self.type = {}

    def __setitem__(self, k, v):
        """
        """
        pass

    def add(self, n, t, w, s=False):
        """
        """
        if self.has_key(n):
            raise AssertionError, "HDL variable " + n + " already exists in this dictionary."
                ##raise AssertionError, hatchNodeErrorString(hatchNode, str(e) + " property not defined.")

        dict.__setitem__(self, n, VerilogNet(self, n, t, w, s))

#-----------------------------------------------------------------
